Generate HDL code for fixed-point filters

Filter Design HDL Coder generates synthesizable, portable VHDL and Verilog code for implementing fixed-point filters designed with MATLAB on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.

Key Features

Generation of synthesizable IEEE 1076 compliant VHDL code and IEEE 1364-2001 compliant Verilog code
Control over generated code content, optimization, and style
Distributed arithmetic and other options for speed vs. area tradeoff and architecture exploration
VHDL and Verilog test-bench generation for quick verification and validation of generated HDL filter code
Simulation and synthesis script generation

The generated VHDL and Verilog code adheres to a clean HDL coding style that enables architects and designers to quickly customize the code if needed. The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation.